1. Field of the Invention
The present invention relates to the capture of digital images. More particularly, the present invention relates to vertical-color-filter detector groups and arrays thereof. More particularly, the present invention relates to arrays of detector groups wherein each of the detector groups is a multi-layer junction structure to ensure that each pixel sensor in the array measures each of the three primary colors (R-G-B) in the same location and image-capture devices such as digital cameras employing such arrays.
2. The Prior Art
Semiconductor devices for measuring the color of light are known in the non-imaging art. These devices have been built with a variety of technologies that depend upon the variation of photon absorption depth and wavelength. Examples are disclosed in U.S. Pat. No. 4,011,016 entitled “Semiconductor Radiation Wavelength Detector” and U.S. Pat. No. 4,309,604 entitled “Apparatus for Sensing the Wavelength and Intensity of Light.” Neither patent discloses either a structure for a three-color integrated-circuit color sensor or an imaging array.
In the imaging art, CCD devices with multiple buried channels for accumulating and shifting photo charges are known. These devices are difficult and expensive to manufacture and have not been practical for three-color applications. U.S. Pat. No. 4,613,895 entitled “Color Responsive Imaging Device Employing Dependent Semiconductor Optical Absorption” discloses an example of such a device. This category also includes devices that use layers of thin film photosensitive materials applied on top of an imager integrated circuit. Examples of this technology are disclosed in U.S. Pat. No. 4,677, 289 entitled “Color Sensor” and U.S. Pat. No. 4,651,001 titled “Visible/Infrared Imaging Device with Stacked Cell Structure.” These structures are also difficult and expensive to produce and have not become practical.
Also known in the imaging art are color-imaging integrated circuits that use a color filter mosaic to select different wavelength bands at different photo sensor locations. U.S. Pat. No. 3,971,065, entitled “Color Imaging Array”, discloses an example of this technology. As discussed in Parluski et al., “Enabling Technologies for a Family of Digital Camera”, 156/SPIE Vol. 2654, 1996 one pixel mosaic pattern commonly utilized in Digital cameras is the Bayer Color Filter Array (CFA) pattern.
Shown in FIG. 1, the Bayer CFA has 50% green pixels arranged in a checkerboard. Alternating lines of red and blue pixels are used to fill in the remainder of the pattern. Color overlay filters are employed to produce the color selectivity between the red, green, and blue sensors. Such sensors have the disadvantage of occupying a relatively large area per pixel as these sensors are tiled together in a plane. As shown in FIG. 2, the Bayer CFA pattern results in a diamond shaped Nyquist domain for green and smaller, rectangular shaped Nyquist domains for red and blue. The human eye is more sensitive to high spatial frequencies in luminance than in chrominance and luminance is composed primarily of green light. Therefore, since the Bayer CFA provides the same Nyquist frequency for the horizontal and vertical spatial frequencies as a monochrome imager, the Bayer CFA improves the perceived sharpness of the digital image.
Mosaic approaches are well known in the art to be associated with aliasing problems due to the sensors being small compared to the spacing between sensors so that the sensors locally sample the image signal, and that the sensors for different colors are in different locations, so that the samples may not align between colors.
As pointed out above in the discussion of CCD color imaging arrays, the semiconductor processes employed in manufacturing arrays can be both difficult and expensive to implement. There are, however, CMOS technologies that are known that may be implemented with less expense and greater ease.
Another type of multiple-wavelength sensor employs more than one sensor in a vertically-oriented group. An example of an early multiple-wavelength vertical-color-filter sensor group for detecting visible and infrared radiation is disclosed in U.S. Pat. No. 4,238,760 issued to Carr, in which a first diode in a surface n-type epitaxial region is responsive to visible light and a second buried region in an underlying n-type substrate is responsive to infrared radiation. Contact to the buried photodiode is made using deep diffusion processes similar to diffusion-under-film collector contact common in bipolar IC processing and for Rcs reduction. The disclosed device has a size of 4 mils square. An alternative embodiment employs V-groove MOS transistor contacts to contact the buried p-type region of the infrared diode.
The device disclosed in the Carr patent has several shortcomings, the most notable being its large area, rendering it unsuitable for the image sensor density requirements of modern imaging systems. The technology employed for contact formation to the buried infrared sensing diode is also not suitable for modern imaging technology or extension to a three-color sensor.
Referring to FIG. 3, many modem CMOS integrated circuit fabrication processes use a “twin-well” or “twin-tub” process in which a P well region 10 and a N well region 12 of doping density of approximately 1017 atoms/cm3 are used in regions within which to make N-channel and P-channel transistors respectively. The substrate material 14 is typically a lightly-doped P-type silicon (1015 atoms/cm3), so P well 10 is not isolated from substrate 14. The N-channel FET 16 formed in P-well 10 includes N+ normal source/drain diffusions 18 at a dopant concentration of >1018 atoms/cm3 and N-type shallow Lightly-Doped-Diffusion (LDD) regions 20 at a concentration of approximately 1018 atoms/cm3. The P-channel FET 22 formed in N well region 12 is similarly constructed using normal P+ source/drain regions 24 and shallow LDD regions 26 of similar dopant concentrations.
Referring to FIG. 4, in an improved process, known as “triple-well”, an additional deep N isolation well 28 is used to provide well isolation between the P well 10 and substrate 14 (1015 atom/cm3 respectively). structures in FIG. 4 corresponding to structures in FIG. 3 are identified by the same reference numerals used in FIG. 3. U.S. Pat. No. 5,397,734 titled “Method of Fabricating a Semiconductor Device Having a Triple-well Structure”, discloses an example of triple-well technology.
Triple-well processes are becoming popular and economical for manufacturing MOS memory (DRAM) devices, since triple-well processes provide effective isolation of dynamic charge storage nodes from stray minority carriers that may be diffusing through the substrate.
A particular example of a three-color visible-light prior art vertical-pixel-sensor group shown in FIG. 5 is disclosed in U.S. Pat. No. 5,965,875 to Merrill. In Merrill, a structure is provided using a triple-well CMOS process including n-well 30 in p-type substrate 32, p-well 34 in n-well 30, and lightly-doped-drain region 36 disposed in p-well 34. The blue, green, and red sensitive PN junctions are seen disposed at different depths beneath the surface of the semiconductor substrate upon which the imager is fabricated.